1. Field of the Invention
The invention relates in general to integrated circuits, and more particularly, to mixed-signal simulation and verification of integrated circuit designs.
2. Description of the Related Art
The evolution toward ultra-deep-submicron and nanometer CMOS technologies has fostered the development of mixed-signal integrated circuits that embed on a single die both complex digital circuitry and high performance analog circuitry. Digital signals are discrete-event signals with discrete values that are at a constant discrete value for a period of time, and then abruptly change to a new discrete value. In digital signals, there only are a very few different discrete values, typically two, ‘true’ and ‘false’ or logic ‘one’ and logic ‘zero’. Analog signals vary continuously meaning that the value of the signal at any point in time may be any value from within a continuous range of values. Analog signals may be discrete-event signals that are represented as piecewise constant versus time, meaning that a signal holds its value for a period of time before jumping to a new value. Alternatively, analog signals may be continuous versus time meaning that its value varies smoothly as a function of time.
The increasing complexity of systems that can be integrated on a single die has lead to design methodologies that allow designers to design and verify a system at an abstract or block diagram level prior to development of the detailed design of the individual blocks. For example, in a top-down design approach, the performance required of individual blocks to meet overall system performance is evaluated before details of the blocks are fully developed. A typical top-down design flow for a mixed-signal integrated system may involve several distinct phases such as, system design, architecture design, cell design, and cell-layout. The design methodology may involve mapping a system level algorithm to a particular architecture that is partitioned into blocks that represent sections of the circuit to be designed simulated and verified as a unit.
A mixed-signal design comprises both digital and analog circuit blocks. Digital circuit blocks may be specified at the behavioral or RTL or gate level using—a digital HDL (hardware description languages) such as Verilog or VHDL. Analog circuit blocks may be specified at the behavioral or transistor-level using Analog or Mixed Signal an HDLs (hardware description language) such as SPICE or Verilog-AMS. For mixed-signal simulation the digital blocks are simulated using a digital HDL representation and the analog blocks are simulated using an Analog or Mixed Signal HDL representation. Verilog-AMS, is an example of an HDL primarily used to support simulation of analog and mixed-signal systems by describing the system to a simulator. SPICE, is an example of HDL used to describe a design at the transistor level of detail. During architecture development in a top-down design methodology, blocks may be represented abstractly, and a single block may include both analog and digital functionality. As the design is refined the demarcation between analog and digital blocks becomes more precisely defined. When simulating a design, IEs (interface elements), whose functionality is describing using Verilog-AMS, also referred to as connect modules; are inserted between analog and digital blocks to transform continuous domain information to discrete domain or vice versa. In order to ensure that simulation accurately represents reality, a connect module typically is modeled in terms of parameters such as impedance and supply voltages.
The simulation of a mixed-signal circuit that includes both digital and analog blocks involves two methods of simulation: event-driven digital simulation as found in logic simulators and continuous-time analog simulation as found in circuit simulators. Digital blocks are simulated using digital simulator, and analog blocks are simulated using an analog simulator. Techniques have been developed to designate which simulation technique is to be used to simulate each block in a design.
In the course of developing a circuit design, a designer may decide to replace a given digital block in the design with an analog block. For example, different versions of a given design block already may have been verified in pure digital or pure analog verification flow. Designers sometimes wish to switch between those different versions (behavioral, gate-level, transistor-level) of a block for Digital Verification Flow (DVF), Analog Verification Flow (AVF), or Analog Mixed-signal Verification Flow (AMSVF) Verification Flow. One typical reason for replacement of a digital block with an analog block is to achieve more accurate simulation results. For example, a digital block may model a circuit component at a more abstract level that provides less detail concerning the actual structure and behavior of the circuit than does its analog counterpart. Accordingly, a simulation using the analog block often will provide more precise and accurate results. During full chip verification it is often a design choice as to whether to switch some blocks of the design from digital to analog so as to simulate the circuit with more accuracy to ensure better yield during subsequent manufacture of the circuit or to improve performance. This replacement of a digital version of a block with an analog version entails a need to inform the simulator of a change in simulation technique to be applied to the block. In addition, assuming that the given digital block to be replaced is connected to another digital block, such replacement also entails a need to specify digital terminals that correspond to terminals of the analog block that is to replace the given digital block. Moreover, a connect module will be inserted between the new analog block and the other digital block in the design.
While prior techniques to replace a digital design block with an analog design block in a circuit design generally have been acceptable, there have been several shortcomings with their use. For example, languages like Verilog-AMS and VHDL-AMS provide capabilities to address these needs, and these languages are supported in simulation tools. However, these languages can be difficult to master, and a designer may not wish modify a pre-verified block for the purpose of performing mixed-signal simulation and verification. Also, in order to use Verilog-AMS, the analog netlist must be expressed in terms of Verilog-AMS. However, it is not uncommon that the analog netlist is specified in a SPICE-like language. Since Verilog and SPICE are two distinct languages in terms of semantics, it can be difficult to switch blocks between them without manual intervention, which can be time consuming and error-prone. Thus, there has been a need for improvement to techniques to replace a digital design block with an analog design block in an integrated circuit design for use in mixed-signal simulation and verification. The present invention meets this need.
Moreover, while prior techniques to insert interface elements in a mixed-signal design generally have been acceptable, there have been shortcomings with their use. For instance, there has been a need for a technique to insert an interconnect element with a behavior that varies with variations of analog circuit parameters. The present invention meets this need.